A new paradigm is proposed by the development of the so-called “chiplet” approach, where a chiplet is an integrated circuit block that has been specifically designed to work with other chiplets to form more complex integrated systems. This approach can be used for System in Package (SiP) (heterogeneous integration) in which the System is subdivided into functional circuit blocks. Chiplets offer a new opportunity for defence electronics, overcoming the limitations of generic components like FPGAs (offering a single solution with limited performances) and ASICs (offering high performances but with high development costs due to the specific development). Chiplet architecture offers an interesting opportunity to reduce the development costs thanks to the reuse of existing blocks and to decrease the manufacturing cost thanks to higher yield compared to large monolithic dies. It may also benefit from use of off-the-shelf chiplets to limit development costs and reinforce the resilience of the supply chain. In addition, chiplets-based architectures are scalable: the addition or removal of chiplets enables the performance and/or functionality adjustment of the SiP.

Chiplet technology in combination with heterogeneous packaging has been widely used in increasing performance of commercial CPUs. The chiplet technology combined with heterogeneous packaging offers the possibility to integrate chiplets processed in different technologies into the same package, thus offering the possibility to develop very compact and innovative System in Package.

This topic aims to explore the development and sharing of a common hardware library of chiplets and their military applications. This require a thorough analysis of possible architectures, and the design of minimum one military application. The proposed architectures should use EU-based technologies where available. Taking in account the existing EU manufacturing facilities and the civil programs such as Chips JU, proposed architecture should address:

• The non-dependence for defence systems to integrate this solution.
• The cost efficiency of the solution for low volume quantities (including NRE).

Particular attention should be placed on the power consumption, as this is an important issue for several applications.
The scalability of the architecture, in other words the possibility to adjust the SiP performances and/or functionalities through the addition or removal of chiplets in the design, should be presented and analysed.
In addition, proposals may address the integration of security features (cybersecurity) in the architecture, especially for protecting the resulting SiP.