It is important to strengthen Europe’s strong position in advanced military IR components and systems. It is key for Europe sovereignty to have a full “EU autonomous” supply chain of IR detectors. The performance of the IR detector modules is driven not only by the IR detector itself but also by Silicon readout integrated circuits (ROIC) technology and components for cooling, if required.

Targeted activities: Activities aiming to create, underpin and improve knowledge, activities aiming to increase interoperability and resilience, studies and design. These activities should be articulated as follows, without exceeding TRL4:

(1) From system requirements to ROIC technology specifications(“Improve knowledge”): The targeted activities must in particular include, for both 2D and 3D ROICs, the collection and analysis of IR system integrators requirements; their translation into 2D and 3D building blocks, the prioritisation of these building blocks such as (and not exclusively) their coverage of future EU defence applications, an inventory of the Silicon nodes and IPs available in a selected EU foundry, and choice of the best one(s) to interface with different detector technologies (both cooled and uncooled) and be compatible with both 2D and 3D architectures.

(2) Identification and qualification of an advanced silicon node (“Improve knowledge”) : Furthermore for conventional 2D advanced ROICs they must include activities aiming at identifying and acquiring (a) new advanced silicon node(s) for future infrared detectors’ read out circuits, such as interface definition and integration constraints with sensing blocks and packaging, both for cooled and uncooled detectors; definition of performance indicators to evaluate technical solutions versus the system integrators’ requirements; test chip design(s) for fabrication and test of 2D advanced functional blocks; characterisation, modelling and reliability activities on test chip specific patterns.

(3) ROICs design, fabrication and functional test (“Improve knowledge” and “Studies”) This will prepare for necessary activities aiming at the electronic design, fabrication and functional test (first characterisations, excluding electro-optics) of (a) first high definition, large format, ultra-small pitch (≤7,5μm) 2D Read Out Circuit(s) with smart functions on this new CMOS platform(s); as well as preparatory studies to enable future ROIC functional routine tests at industrial level. When relevant some tests by system providers should be performed on the communication protocols based on the raw read out circuits.

(4) Preparatory work of 3D technology acquisition (“Improve knowledge”) on the selected node for 3D ROICs with increased functionalities at detector and pixel level will also be covered: exploration of 3D ROIC architectures allowing implementation of add-on functionality in a second layer, such as higher scene dynamics/reduced pixel pitches, in-situ image compression for large arrays/high frame rates, combination functions of passive/active imaging, event-based computing, in situ machine learning.