The overall objective of this challenge is to explore solutions (starting at TRL 1/2) that will have a drastic impact on decreasing the power consumption of any smart edge device, but specially for Edge Processing and memories, Edge Sensing and Imaging, Edge Communication and Edge Power Management. The proposed solutions should start at TRL 1-2 and reach TRL 3-4.

The projects, supported under this Challenge are expected to address one or more of the following aspects:

• fundamental issues like heat dissipation at nanoscale that has turned out to be the most critical bottleneck in information processing covering the design of a device from the understanding of the physics and the nanoscale thermal transport at component level to circumvent the “heat valley”, selecting the materials and process solutions.
• demonstration of the potential of the developed technologies for energy savings and contained environmental footprint towards responsible smart edge devices.

The proposed developments may cover (amongst others):

At Design level.

• Computer modelling based on the fundamental understanding of heat transport across layers and interfaces, harvesting fluctuations instead of fighting them for computing or the use of different state variables, e.g., spins, photons, phonons or mechanical switches, instead of charge.
• Analysis of the dissipation mechanisms in signal transmission and conversion, heat removal from hot spots in components and circuits, potential for energy conversion at the nano-scale, etc.

At Materials/Process levels:

• Novel or unique electrical, mechanical and optical interconnections or other switching mechanisms
• Efficient heat dissipation new materials for in-chip heat dissipation, e.g., 2D materials
• Embedding energy harvesters in the final devices and/or circuits
• Effective 3D multi-die heterogeneous integration including advanced packaging, heterogeneous integration, and modular design of components (such as chiplets)

At Device/Architecture levels:

• Molecular electronic circuits
• Beyond CMOS. Non mainstream semiconductor transistors including a plausible circuit concept, e.g., single electron transistors.
• Novel non-von Neumman architectures and alternative processing approaches