Open-source EDA tools development

Opened

Programme Category

EU Competitive Programmes

Programme Name

Chips Joint Undertaking (Chips JU)

Programme Description

The Chips Joint Undertaking (Chips JU) is a pioneering initiative committed to catalysing research, development, and manufacturing capabilities across Europe. In this section, we delve into the key facets of Chips JU and its mission to shape the semiconductor future of the European Union.

The Chips Joint Undertaking (JU) supports research, development, innovation, and future manufacturing capacities in the European semiconductor ecosystem.

Programme Details

Identifier Code

HORIZON-JU-CHIPS-2025-IA-EDA-two-stage

Call

Open-source EDA tools development

Summary

A key objective of the Chips Act under the Chips for Europe Initiative is the ‘building up of advanced design capacity for integrated semiconductor technologies’.Τhe Initiative shall integrate ‘new design facilities with extended libraries and electronic design automation (EDA) tools’ into a virtual design platform, that will make available a number of open-source tools. Chip design is a vital element in the semiconductor value chain and open-source Electronic Design Automation (EDA) tools can be key drivers for innovation in this sector by enabling researchers and developers to experiment with new algorithms, architectures, and methodologies.

Detailed Call Description

The technology Readiness Level is targeted TRL at the end of projects is between 7 and 8.

Each proposal must address only one of the following three streams:

  • Digital SoC design. The overall ambition of this stream is to ensure a comprehensive and stable digital design flow in more mainstream nodes (65-28nm). Improvement of tools in more mature nodes is also within scope of this stream. To this end a baseline for the quality of results currently achievable with current state-of-the-art open-source tools needs to be determined.
  • Analogue and mixed-signal design. The overall ambition of this stream is the development of a full analogue/mixed-signal design flow. The emphasis should extend beyond improving existing tools to include the adoption of innovative approaches and new paradigms or
  • Productivity, interoperability, and verification. The overarching aim of this stream is to enhance productivity by adopting innovative design approaches and ensuring seamless data exchange between tools. This will be complemented by the development of robust verification processes that accommodate diverse methodologies and effectively tackle the increasing complexity of modern chip design.

Results stemming from this call must be well documented and widely disseminated. Precise documentation, user manuals as well as video tutorials must be made available. Selected consortia must develop teaching materials and courses with open resources and examples based on the developed/improved open-source EDA tools, accessible to academic institutions across the EU and suitable for self-study by individuals. To this end, collaboration with initiatives such as EUROPRACTICE is encouraged.

Consortia must actively engage with the Platform Coordination Team of the Chips Act’s Design Platform to integrate their tools into the platform’s design flows. Proposals must outline a clear strategy for engaging with relevant foundries to secure access to the required PDKs.
Proposals should clearly specify the applicable OSI-approved open-source license for all results. Proposals must also include a sustainability plan for results following the end of the project.

Call Total Budget

€20.000.000

Financing percentage by EU or other bodies / Level of Subsidy or Loan

The Chips JU estimates that an EU contribution of between €6.000.000 and €7.000.000 per project would allow these outcomes to be addressed appropriately. It is expected that 3 consortia will be selected.

The maximum contribution per partner in a project is limited to 40% of the total EU funding for the project.

The maximum EU Contribution as percentage of the eligible cost for the topic HORIZON-JU-CHIPS-2025-IA-EDA-two-stage is:

  • Large Enterprise (for profit non-SME) – 20%
  • SME (for profit SME) – 30%
  • University/Other (not for profit) – 50%

Thematic Categories

  • Information Technology
  • Research, Technological Development and Innovation
  • Small-Medium Enterprises and Competitiveness

Eligibility for Participation

  • Businesses
  • Educational Institutions
  • Non Profit Organisations
  • Other Beneficiaries
  • Private Bodies
  • Small and Medium Enterprises (SMEs)

Eligibility For Participation Notes

There are specific eligibility criteria relevant to each KDT JU Participating State listed in the Chips Joint Undertaking (Chips JU) Work Programme 2023-2027. Participation is limited to legal entities established in EU Member States, Norway, Iceland, Associated Countries, OECD and Mercosur countries (see Annex 1 of the WP General Annexes for details).

Eligibility conditions are described in Annex 1 “HORIZON Europe conditions applicable to Chips JU” of the WP General Annexes 2023-2027.

For detailed information about the eligibility conditions for each call, please visit the Chips Joint Undertaking (Chips JU) Work Programme 2023-2027.

Call Opening Date

04/03/2025

Call Closing Date

17/09/2025

EU Contact Point

CHIPS JU

Τelephone: +32 2 221 81 02
Email: enquiries@chips-ju.europa.eu
Address: Chips JU, TO 56 -5/5, 1049, Brussels, Belgium